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14-11-2009, 05:29 PM
Post: #1
Chip Morphing Technology
the technology is part of a built-in self-repair system that constantly monitors a chipâ„¢s functionality. eFUSE works by combining software algorithms and microscopic electrical fuses, opposed to laser fuses, to produce chips that can regulate and adapt their own actions in response to changing conditions and system demands

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14-06-2010, 11:34 AM
Post: #2
RE: Chip Morphing Technology
can u plz send me full documents on chip morphing to sanjuram666[at]gmail.com

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14-06-2010, 02:30 PM
Post: #3
RE: Chip Morphing Technology
Chip Morphing Technology
chip morphing technology is a new technology introduced by IBM which is said to enable a new class of semiconductor products that can monitor and adjust their functions to improve their quality, performance and power consumption.
The eFUSE technology combines unique software algorithms and microscopic electrical fuses. These chips adapt and regulate their actions depending on the conditions and system demands. eFUSE can even dynamically sense that a chip needs tune up eFUSE can alter the configuration and efficiency of circuitry to enhance performance or avoid a potential problem. The eFUSE eFUSE is part of a built-in self-repair system that constantly monitors a chipâ„¢s functionality. Whenever it detects an imperfection, it takes action by tripping inexpensive, simple electrical fuses. It can control the local voltage if it detects a chip is malfunctionbecause individual circuits are running too fast or too slow.

for more details, refer these links:
http://www.xbitlabs.com/news/other/displ...63921.html
http://vr-zone.com/print/ibm-efuse-chip-.../1046.html

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18-06-2010, 05:49 PM
Post: #4
RE: Chip Morphing Technology
pls send chip morphing technology

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18-06-2010, 06:55 PM
Post: #5
RE: Chip Morphing Technology

Introduction

In computer engineering the trade-off (reduce cost) has traditionally been between performance, measured in instructions per second, and price. Because of fabrication technology, price is closely related to chip size and transistor count. With the emergence of embedded systems, a new tradeoff has become the focus of design. This new tradeoff is between performance and power or energy consumption. The computational requirements of early embedded systems were generally more modest, and so the performance-power tradeoff tended to be weighted towards power. "High performance" and "energy efficient" were generally opposing concepts.

However, new classes of embedded applications are emerging which not only have significant energy constraints, but also require considerable computational resources. Devices such as space rovers, cell phones, automotive control systems, and portable consumer electronics all require or can benefit from high-performance processors. The future generations of such devices should continue this trend.

Processors for these devices must be able to deliver high performance with low energy dissipation. Additionally, these devices evidence large fluctuations in their performance requirements. Often a device will have very low performance demands for the bulk of its operation, but will experience periodic or asynchronous "spikes" when high-performance is needed to meet a deadline or handle some interrupt event. These devices not only require a fundamental improvement in the performance power tradeoff, but also necessitate a processor which can dynamically adjust its performance and power characteristics to provide the tradeoff which best fits the system requirements at that time.

PROCESSOR PERFORMANCE

These motivations point to three major objectives for a power conscious embedded processor. Such a processor must be capable of high performance, must consume low amounts of power, and must be able to adapt to changing performance and power requirements at runtime.

The objective of this seminar is to define a micro-architecture which can exhibit low power consumption without sacrificing high performance. This will require a fundamental shift to the power-performance curve presented by traditional microprocessors. Additionally, the processor design must be flexible and reconfigurable at run-time so that it may present a series of configurations corresponding to different tradeoffs between performance and power consumption.

MORPH


These objectives and motivations were identified during the MORPH project, a part of the Power Aware Computing / Communication (PACC) initiative. In addition to exploring several mechanisms to fundamentally improve performance, the MORPH project brought forth the idea of "gear shifting" as an analogy for run-time reconfiguration. Realizing that real world applications vary their performance requirements dramatically over time, a major goal of the project was to design microarchitectures which could adjust to provide the minimal required performance at the lowest energy cost. The MORPH project explored a number of microarchitectural techniques to achieve this goal, such as morphable cache hierarchies and exploiting bit-slice inactivity. One technique, multi-cluster architectures, is the direct predecessor of this work. In addition to microarchitectural changes, MORPH also conducted a survey of realistic embedded applications which may be power constrained. Also, design implications of a power aware runtime system were explored

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