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14-11-2009, 05:29 PM
Post: #1
Chip Morphing Technology
the technology is part of a built-in self-repair system that constantly monitors a chipâ„¢s functionality. eFUSE works by combining software algorithms and microscopic electrical fuses, opposed to laser fuses, to produce chips that can regulate and adapt their own actions in response to changing conditions and system demands

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14-06-2010, 11:34 AM
Post: #2
RE: Chip Morphing Technology
can u plz send me full documents on chip morphing to sanjuram666[at]gmail.com
14-06-2010, 02:30 PM
Post: #3
RE: Chip Morphing Technology
Chip Morphing Technology
chip morphing technology is a new technology introduced by IBM which is said to enable a new class of semiconductor products that can monitor and adjust their functions to improve their quality, performance and power consumption.
The eFUSE technology combines unique software algorithms and microscopic electrical fuses. These chips adapt and regulate their actions depending on the conditions and system demands. eFUSE can even dynamically sense that a chip needs tune up eFUSE can alter the configuration and efficiency of circuitry to enhance performance or avoid a potential problem. The eFUSE eFUSE is part of a built-in self-repair system that constantly monitors a chipâ„¢s functionality. Whenever it detects an imperfection, it takes action by tripping inexpensive, simple electrical fuses. It can control the local voltage if it detects a chip is malfunctionbecause individual circuits are running too fast or too slow.

for more details, refer these links:
http://www.xbitlabs.com/news/other/displ...63921.html
http://vr-zone.com/print/ibm-efuse-chip-.../1046.html

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18-06-2010, 05:49 PM
Post: #4
RE: Chip Morphing Technology
pls send chip morphing technology
18-06-2010, 06:55 PM
Post: #5
RE: Chip Morphing Technology

Introduction

In computer engineering the trade-off (reduce cost) has traditionally been between performance, measured in instructions per second, and price. Because of fabrication technology, price is closely related to chip size and transistor count. With the emergence of embedded systems, a new tradeoff has become the focus of design. This new tradeoff is between performance and power or energy consumption. The computational requirements of early embedded systems were generally more modest, and so the performance-power tradeoff tended to be weighted towards power. "High performance" and "energy efficient" were generally opposing concepts.

However, new classes of embedded applications are emerging which not only have significant energy constraints, but also require considerable computational resources. Devices such as space rovers, cell phones, automotive control systems, and portable consumer electronics all require or can benefit from high-performance processors. The future generations of such devices should continue this trend.

Processors for these devices must be able to deliver high performance with low energy dissipation. Additionally, these devices evidence large fluctuations in their performance requirements. Often a device will have very low performance demands for the bulk of its operation, but will experience periodic or asynchronous "spikes" when high-performance is needed to meet a deadline or handle some interrupt event. These devices not only require a fundamental improvement in the performance power tradeoff, but also necessitate a processor which can dynamically adjust its performance and power characteristics to provide the tradeoff which best fits the system requirements at that time.

PROCESSOR PERFORMANCE

These motivations point to three major objectives for a power conscious embedded processor. Such a processor must be capable of high performance, must consume low amounts of power, and must be able to adapt to changing performance and power requirements at runtime.

The objective of this seminar is to define a micro-architecture which can exhibit low power consumption without sacrificing high performance. This will require a fundamental shift to the power-performance curve presented by traditional microprocessors. Additionally, the processor design must be flexible and reconfigurable at run-time so that it may present a series of configurations corresponding to different tradeoffs between performance and power consumption.

MORPH


These objectives and motivations were identified during the MORPH project, a part of the Power Aware Computing / Communication (PACC) initiative. In addition to exploring several mechanisms to fundamentally improve performance, the MORPH project brought forth the idea of "gear shifting" as an analogy for run-time reconfiguration. Realizing that real world applications vary their performance requirements dramatically over time, a major goal of the project was to design microarchitectures which could adjust to provide the minimal required performance at the lowest energy cost. The MORPH project explored a number of microarchitectural techniques to achieve this goal, such as morphable cache hierarchies and exploiting bit-slice inactivity. One technique, multi-cluster architectures, is the direct predecessor of this work. In addition to microarchitectural changes, MORPH also conducted a survey of realistic embedded applications which may be power constrained. Also, design implications of a power aware runtime system were explored

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22-06-2010, 07:43 PM
Post: #6
RE: Chip Morphing Technology
plz send me everything about CHIP MORPHING TECHNOLOGY to sanjuram666[at]gmail.com .everything including PPT and doc. Thanks .
25-06-2010, 09:18 PM
Post: #7
RE: Chip Morphing Technology
plz send me everything about chip morphing
03-07-2010, 11:44 AM
Post: #8
RE: Chip Morphing Technology
:heart:Chip Morphing Technology
04-07-2010, 01:28 PM
Post: #9
RE: Chip Morphing Technology
needs the seminar report on " Chip Morphing Technology"
04-07-2010, 03:53 PM
Post: #10
RE: Chip Morphing Technology
For more details, visit these links:
http://www.physorg.com/pdf613.pdf
http://en.wikipedia.org/wiki/EFUSE

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13-07-2010, 11:01 PM
Post: #11
RE: Chip Morphing Technology
Hi,i am Bhagyashri.I want seminar on "CHIP MORPHING TECHNOLOGY" based on INFORMATION TECHNOLOGY.So,please send me the seminar report on "CHIP MORPHING TECHNOLOGY"
16-07-2010, 11:53 AM
Post: #12
RE: Chip Morphing Technology
Please send me the seminar on CHIP MORPHING TECHNOLOGY based on INFORMATION TECHNOLOGY.
16-07-2010, 12:24 PM
Post: #13
RE: Chip Morphing Technology
please,send me the seminar on CHIP MORPHING TECHNOLOGY.
16-07-2010, 03:05 PM
Post: #14
RE: Chip Morphing Technology
please,send me full seminar on CHIP MORPHING TECHNOLOGY.
18-07-2010, 02:05 PM
Post: #15
RE: Chip Morphing Technology
Please send me the seminar on CHIP MORPHING TECHNOLOGY.
THANKS.
29-07-2010, 04:31 PM
Post: #16
RE: Chip Morphing Technology
send full report and ppt on chip morphing
07-08-2010, 10:21 PM
Post: #17
RE: Chip Morphing Technology
my seminar topic is chip morphing,please give me more information about it
17-09-2010, 04:07 PM
Post: #18
RE: Chip Morphing Technology
hi
the following link can help you to get more information on chip morphing

http://www.seminarprojects.com/Thread-ch...ing--10342
18-12-2010, 03:00 PM
Post: #19
RE: Chip Morphing Technology

.ppt  morphing technology.ppt (Size: 1.4 MB / Downloads: 118)
MORPHING TECHNOLOGY



CONTENTS
Introduction
How morphing works ?
Types of morphing
Application of morphing
Benefits of morphing
conclusion

WHAT IS MORPHING ?
The term morphing stands for metamorphosing and refers to an animation technique in which one graphical object is gradually turned into another.
Simply speaking the tween of an object in between two existing objects is called morphing.

WHAT IS TWEENING ?
Tweening means to insert between other things or parts, or to estimate values of a function between two known values.


Ex we can tween a straight line between two straight lines.
HOW MORPHING WORKS?
The morph between command is only active when exciting two objects are selected at the same time.
It performs a linear morph between the two objects with a specified number of interim steps.

The working of morphing based on the algorithm which described below.
MORPHING ALGORITHIM
WARP

COLOR DISSOLVE

MAPPING

WARP
It is the process of rotating, squeezing ,stretching or shearing of image pixels so that the source image matches with the target image in a sequence.

Ex:-image is warped using a straight line using warped vector

COLOR DISSOLVE
Before we present the formulation of color dissolve, let us discuss some basics! A particular color is considered to be a vector in the orthogonal axes system as shown in the figure below. The three axes represent the true red, green and blue colors, commonly known as RGB space
12-03-2011, 02:22 PM
Post: #20
RE: Chip Morphing Technology

.docx  Chip Morphing.docx (Size: 12.96 KB / Downloads: 47)
IBM Intros “Chip Morphing Technology”
International Business Machines Friday unveiled its new “chip morphing technology” that would, as the company said, enable a new class of semiconductor products that can monitor and adjust their functions to improve their quality, performance and power consumption without human intervention.
The patented technology, called “eFUSE”, combines unique software algorithms and microscopic electrical fuses to produce chips that can regulate and adapt their own actions in response to changing conditions and system demands. By dynamically sensing that a chip needs a “tune-up”, eFUSE can alter the configuration and efficiency of circuitry to enhance performance or avoid a potential problem. This autonomic capability is expected to change the way chips are designed, manufactured and integrated into computers, cell phones, consumer electronics and other products.
“eFUSE reroutes chip logic, much the way highway traffic patterns can be altered by opening and closing new lanes,” said Dr. Bernard Meyerson, IBM Fellow, vice president and chief technologist, IBM Systems and Technology Group.
eFUSE is part of a built-in self-repair system that constantly monitors a chip’s functionality. If an imperfection is detected, this innovative technology “instinctively” initiates corrective actions by tripping inexpensive, simple electrical fuses that are designed into the chip at no additional cost. The activated fuses help the chip control individual circuit speed to manage power consumption and repair unexpected, and potentially costly flaws. If the technology detects that the chip is malfunctioning because individual circuits are running too fast or too slow, it can “throttle down” these circuits or speed them up by controlling the appropriate local voltage.
“Our work with innovative technologies like eFUSE is a result of IBM's commitment to investing in fundamental research and development, as well as to creating an environment that values and stimulates innovation,” Mr. Meyerson added.
The morphing technology also will optimize and tailor the performance and capabilities of a chip to meet an individual customer’s product needs in response to changing end-user or software demand. Customers further benefit from the versatility of eFUSE as the morphing can be repeated several times – even after the chip has been packaged and shipped in a product.
Invented and refined by IBM scientists and engineers, eFUSE achieves a goal pursued by chip designers for many years by putting to positive use the phenomena of “electromigration”, the company said.
This phenomena has traditionally been detrimental to chip performance and was avoided — even at significant cost and effort. IBM has perfected a technique that harnesses electromigration and uses it to program a fuse without damaging other parts of the chip. Previous implementations of on-chip fuse technology in the industry often involved rupturing fuses, which had resulted in unwanted performance and reliability problems.
Both versatile and adaptable, eFUSE is being implemented to support a variety of applications, such as high-performance microprocessors based on IBM's Power Architecture, including Power5 and other chips used in IBM eServer systems, as well as low-power IBM silicon germanium (SiGe) chips. eFUSE-enabled chips also are available to IBM foundry customers.
IBM also is leveraging the self-managing function of eFUSE in all 90nm custom chips, including those designed with IBM’s advanced embedded DRAM technology.
eFUSE is technology independent, does not require introduction of new materials, tools or processes, and is in production today at IBM’s 300mm facility in East Fiskhill, New York and 200mm plant in Burlington, Virginia.
24-03-2011, 11:07 PM
Post: #21
RE: Chip Morphing Technology
SleepyIdeaUndecidedAngelDodgy
04-05-2011, 12:51 PM
Post: #22
RE: Chip Morphing Technology
hi
you can refer these pages to get the details on chip morphing technology

http://www.seminarprojects.com/Thread-ch...technology

http://www.seminarprojects.com/Thread-ch...ing--15851

http://www.seminarprojects.com/Thread-ch...ogy?page=2
23-06-2011, 06:18 PM
Post: #23
RE: Chip Morphing Technology
i badly need a seminar report on chip morphing technology...pls do send me..my email id is reshma12370[at]yahoo.com..thnx
30-06-2011, 09:43 AM
Post: #24
RE: Chip Morphing Technology
Hi refer the link for more details of Chip Morphing Technology
http://www.seminarprojects.com/Thread-ch...technology
http://www.seminarprojects.com/Thread-ch...ogy?page=5
http://www.physorg.com/pdf613.pdf
http://en.wikipedia.org/wiki/EFUSE
09-07-2011, 03:34 PM
Post: #25
RE: Chip Morphing Technology
CHIP MORPHING
This seminar discusses results from the project called morph where the goal was to develop a micro architecture that can adapt it intrinsic performance dynamically. By observing the power dissipation, reducing the performance characteristics thus reduces the power even faster, resulting in greatly improved performance/ watt characteristics . these Techniques such as voltage scaling and as such add an extra time “gear” which real embedded system manipulate. In addition to the micro architecture work, the paper also briefly discuss the driving application to be used in its evaluation, namely planetary rovers and a discussion of some of the runtime software considerations that will be necessary to work through to make the “gear changing” a usable piece of technology. This paper has attempted to introduce the main concepts in the Morph project, an attempt to approach low power embedded system in a novel way - by attacking power consumption during those frequent times when less than peak performance is needed. The approach taken is that of adding an energy/performance “gear” - in such low performance demanding times, the intrinsic performance of the computer can be throttled back, and done so in ways where the energy per operation performed drops precipitously. The result should be a substantial improvement in the performance energy curve.
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