01052012, 11:59 AM


DESIGN AND SIMULATION OF 4BIT GRAY TO BINARY CODE CONVERTOR

DESIGN AND SIMULATION OF 4BIT GRAY TO BINARY CODE CONVERTOR
THEORY:
The gray code belongs to a class of codes called minimumchange codes, in which only one bit in the code group changes when moving from one step to the next. The gray code is non â€“weighted code. The gray code is a reflective digital code which has a special property of containing two adjacent code numbers that differ by only one bit.
During conversion from gray to binary some of the important steps always be taking into the account that the first binary bit (MSB) is the same as that of the first gray code bit. If the second gray bit is 0, the second binary bit is the same as that of the first binary; if the second gray bit is 1; the second binary bit is the inverse of its first binary bit. The same process is repeated for each successive bit.
VHDL CODE OF 4BIT GRAY TO BINARY CODE CONVERTOR:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gray is
Port ( G : in STD_LOGIC_VECTOR (3 downto 0);
B : out STD_LOGIC_VECTOR (3 downto 0));
end gray;
architecture dataflow of gray is
begin
B(3)<=G(3);
B(2)<=G(3) xor G(2);
B(1)<=G(3) xor G(2) xor G(1);
B(0)<=G(3) xor G(2) xor G(1) xor G(1);
end Dataflow;
CONCLUSION:
After getting the test bench waveform and RTL schematic of the required experiment ( gray to binary converter) the program is successfully downloaded to the FPGA kit. 


