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13-08-2012, 02:59 PM
Post: #1
Low-Power and Area-Efficient Carry Select Adder full report
Low-Power and Area-Efficient Carry Select Adder



.pdf  Low-Power and Area-Efficient Carry Select Adder.pdf (Size: 280.6 KB / Downloads: 260)

INTRODUCTION

DESIGN of area- and power-efficient high-speed data path logic
systems are one of the most substantial areas of research in VLSI
system design. In digital adders, the speed of addition is limited by the
time required to propagate a carry through the adder. The sum for each
bit position in an elementary adder is generated sequentially only after
the previous bit position has been summed and a carry propagated into
the next position.
The CSLA is used in many computational systems to alleviate the
problem of carry propagation delay by independently generating multiple
carries and then select a carry to generate the sum [1]. However,
the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA) to generate partial sum and carry by considering
carry input    and  , then the final sum and carry are
selected by the multiplexers (mux).
The basic idea of this work is to use Binary to Excess-1 Converter
(BEC) instead of RCA with    in the regular CSLA to achieve
lower area and power consumption [2]–[4]. The main advantage of this
BEC logic comes from the lesser number of logic gates than the
29-10-2012, 11:53 AM
Post: #2
RE: Low-Power and Area-Efficient Carry Select Adder full report
to get information about the topic "low power and area efficient carry select adder" full report ppt and related topic refer the link bellow

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16-03-2013, 10:32 PM
Post: #3
RE: Low-Power and Area-Efficient Carry Select Adder full report
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18-03-2013, 10:40 AM
Post: #4
RE: Low-Power and Area-Efficient Carry Select Adder full report
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31-03-2013, 11:21 PM
Post: #5
RE: Low-Power and Area-Efficient Carry Select Adder full report
i want full documntation for low power clsa can any one post please
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